A general storage device system includes a host interface to follow a widely-used storage device protocol, such as an Advanced Technology Attachment (ATA) protocol and a Small Computer System Interface (SCSI) protocol, non-volatile recording media including a disk, a flash memory, and the like, a controller to control the non-volatile recording media, a processor to manage the entire operation of the system, and a memory to store the code and data of the processor.
The flash memory is a non-volatile memory in which the stored data does not disappear and is maintained even when power is not supplied, and provides a function of electrically erasing and rewriting the whole or a part of a chip. In deletion of the data stored in the flash memory, deletion of all data on the chip and deletion of a block unit are possible, but deletion of a byte unit is impossible.
The flash memory is a semiconductor memory that electrically operates, consumes a small amount of power, is small, and is resistant to physical shock or vibration, when compared with existing storage media including a physical component, such as a disk. Due to these advantages, the flash memory is widely used for storage media of portable electronic devices including a digital camera, a portable multimedia player, a cellular phone, a personal digital assistant (PDA), and the like, or recording media of portable storage devices such as a Universal Serial Bus (USB) disk and a Multi Media Card (MMC) memory card. Also, currently, the flash memory attracts attention as a storage device of a general computer system due to high integration, a drop in price, and high performance by a multi-chip parallel processing scheme.
However, the flash memory may not support in-pace update, and has a limit that an erase operation performed in a unit that is greater than the unit of the write operation is required to be performed in advance. Also, the maximum number of erase operations is predefined for each block that is the unit of the erase operation. Also, since a performance gap between a read operation and a write operation is great, the read speed is very high while the write speed is relatively low.
Due to these limits, the logical address space seen by a host differs from the actual physical address space of the flash memory in a flash memory-based storage device, differently from a hard disk drive using, as the recording media, a magnetic disk that may support in-place update, and the like. Generally, when a host write operation is performed, even if a logical address is identical to the logical address previously used for writing, the write is performed in a different physical address in which an erase operation is already done, and when a host read operation is performed, a translation table being maintained for looking up a physical address in which data of a given logical address is actually located is used. A software layer in charge of such address translation of the flash memory-based storage device is referred to as a Flash Translation Layer (FTL).
The FTL may be generally classified into a sector level translation scheme, in which translation is performed in a sector unit that is the unit of the read and write operation of the host interface, and a block level translation scheme, in which translation is performed in a block unit that is the unit of the erase operation of the flash memory, depending on the translation unit. However, only the size of a translation table varies depending on whether the translation unit is big or small, and still, the translation table is required to be maintained in the memory or the flash memory and referring to the translation table is essential for the read operation.
In addition to the basic address translation, functions performed in the FTL include garbage collection, wear leveling, and the like. The garbage collection is performed for collecting physical sectors having become invalid through a host write operation in the corresponding logical address and restoring them to be writable ones by performing the erase operation. The wear leveling is performed for increasing the life of the entire storage device by balancing the number of times each erase unit is erased.
FIG. 1 is a diagram illustrating a configuration of a flash memory-based storage device according to a conventional art.
As illustrated in FIG. 1, a general flash memory-based storage device includes a host interface 150, a flash memory controller 160, a processor 110, a memory 140, and FTL software 120. When a read operation is processed, the FTL 120 executed in a processor receives a host request including a start sector address and the number of sectors, transforms the host request into a flash memory request including a block number, a sector number in a block, and the number of sectors via reference to a translation table 130 that is maintained in the memory 140 (or in which only a necessary portion of the table is read into the memory 140 when the translation table is maintained in the flash memory), and operates the flash memory controller 160. The data read from the flash memory is transmitted to the host interface 150 via the memory 140 or directly through the First-In First-Out (FIFO).
Also, in the flash memory-based storage devices, the memory is used not only as storage means for storing the code and data of the processor and the translation table of the FTL, but also as a write buffer for improving host write performance. Generally, the low write performance comes from the characteristics of the flash memory that a write operation is slower than a read operation and an erase operation is performed prior to the write operation. When the write buffer is used, however, processing completion is first reported to a host after completing data transmission, and then the actual write operation to the flash memory is performed in the background with hiding the low flash memory write performance. In this case, some data required for processing a read request may exist in the write buffer. Since the data in the write buffer is more up-to-date than the data in the flash memory, the data in the write buffer is required to be transmitted to the host.
In the conventional systems, the processor is fully involved in the host read request processing and the data merging for the write buffer and the flash memory, which is the main cause of the low read performance. In the storage device systems, however, the processor usually operates at a relatively low speed, compared with exclusive logical circuits including a data transmission path, a host interface, a recording media controller, and the like, and hence is a bottleneck that limits host read performance. Also, since the processor necessarily performs other functions of the FTL, that is, management functions including garbage collection, wear leveling, and the like, the processing of a read request may not immediately start when the read request is received while the processor performs these functions, resulting in a significant increase in the processing time. Moreover, in the conventional flash memory-based storage devices using the write buffer, since the processor is in charge of merging the data existing in the write buffer with the data in the flash memory on a sector basis, the amount of operations of the processor increases, and the read performance is more degraded.
Accordingly, a system for processing a read request that allows the processing of a read request of a host interface for a flash memory without the direct intervention of a processor and allows data merging when the data is fragmented in a write buffer is disclosed in the present invention.